1. Field of the Invention
The present invention relates to a pattern inspection apparatus, a pattern inspection method, and a manufacturing method of a semiconductor device.
2. Related Background Art
In recent years, die-to-database inspection is used as an inspection method for a circuit pattern of a semiconductor. This is a method of comparing CAD data with an SEM (Scanning Electron Microscope) image of a circuit pattern obtained by scanning a wafer with an electron beam to detect a secondary electron by use of a scanning electron microscope, thereby inspecting a circuit pattern shape or a deviation amount from the CAD data.
However, since the inspection using an electron beam requires a long time, an increase in speed is strongly demanded. Factors of the long inspection time include a time required to perform electron beam scanning and acquire an SEM image and a moving time of a stage. To reduce such times, there is adopted a method of collectively acquiring SEM images in a wide field by expanding a scan area of an electron beam to reduce the number of times of moving the stage or a method of increasing an electron beam scan speed to rapidly acquire each SEM image.
However, when the scan area is expanded, an optical distortion as Seidel's five aberrations is increased in proportion to the third power of a size of the scan area, and an image nonlinearly largely distortions at an end portion of the scan area.
Further, a deflector requires a large power (a voltage in an electrostatic deflector or a current in a magnetic field deflector) to deflect a beam in proportion to expansion of the scan area. Furthermore, when a scan speed is increased, a burden imposed on an electrical circuit used in a deflection system is largely increased, and a distortion of an electric signal waveform that is input to the deflector to defect a beam is increased, whereby an SEM image from the scan area is locally nonlinearly distorted.
When an SEM image including such a nonlinear distortion is compared with CAD data for inspection, a deviation amount from the CAD data is increased in a region where the distortion occurs, and a pseudo defect with which a normal position is determined as a defect is disadvantageously generated.
To solve the problem, a method of performing scanning to that such a distortion is cancelled out is proposed (e.g., Japanese patent laid open (kokai) No. 2005-277395). This is a method of electrically correcting a shape of a scan area by adjusting an electrical signal (a voltage in an electrostatic deflector or a current in a magnetic field deflector) inputted to a deflector because a nonlinear image distortion cannot be corrected by affine transformation or a function.
However, the method disclosed in Japanese patent laid open (kokai) No. 2005-277395 has a problem that unstableness of an electrical circuit occurs and a distortion cannot be sufficiently corrected due to an increase in burden on the electrical circuit caused by expansion of a scan area and an increase in scan speed explained above.
On the other hand, there is proposed a method in which CAD data are divided, the CAD data are corrected with respect to each divided region by using a measurement result of a pattern position obtained by a highly accurate coordinate measuring instrument, the respective corrected regions are combined to create inspection data, and the created inspection data are compared with a pattern (e.g., Japanese patent laid open (kokai) No. 2006-215528, especially FIG. 9).
However, according to the method disclosed in Japanese patent laid open (kokai) No. 2006-215528, although displacement of a formed pattern can be corrected, a distortion of an image cannot be corrected since there is no means to detect a distortion of an SEM image. Moreover, according to the method disclosed in Japanese patent laid open (kokai) No. 2006-215528, since CAD data are divided and each divided CAD data is corrected, continuity of the divided CAD data at a boundary portion must be maintained. Therefore, there is a problem that a nonlinear distortion that locally occurred cannot be corrected.
Besides, there is also proposed a method of correcting deformation of a pattern image by using positional data obtained from a reference mark formed outside an inspection pattern on a wafer (e.g., Japanese patent laid open (kokai) No. 63 (1988)-138921). According to this method, since the reference mark must be necessarily provided on the wafer, and many reference marks are required to improve a correction accuracy as shown in FIG. 16 in Japanese patent laid open (kokai) No. 63 (1988)-138921. In addition, in this method, data of a design pattern are converted into dots to correct deformation of an image. However, this method has little practicability at the present day because a design data size of a VLSI is explosively increased in recent years, a huge amount of processing time is thereby required for conversion into dots, and an unrealistic time and a throughput of a computer are required when a wide inspection area is a target.